Nov 6, 2016 - INTRODUCTION 7 3. MULTIPLICATION ALGORITHM 8 4.PROCEDURE: 11 PROJECT VERILOG CODE 15 TEST BENCH 16 7.OUTPUT: 19 8.

After 34816 clock cycles, the matrix multiplication for the matrix with size 32x32 is completed and the signal “dataready” is asserted high. It is reasonable because it would take 32 cycles to calculate each matrix component of the output matrix C.

There are also 2 cycles which are saving data and writing data to buffer C for each matrix component. Thus, there are 34 clock cycles being used to calculate one component of matrix C. The size of matrix C is 32x32, then we have the matrix multiplication time is 32x32x34 = 34816 cycles.